Over the past 30 years, anti-fuse technology has attracted significant attention of many inventors, IC designers and manufacturers. An anti-fuse is a structure alterable to a conductive state, or in other words, an electronic device that changes state from not conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. There have been many attempts to develop and apply anti-fuses in microelectronic industry, but the most successful anti-fuse applications to date can be seen in FGPA devices manufactured by Actel and Quicklogic, and redundancy or option programming used in DRAM devices by Micron. Anti-fuse technology is well known in the art, and example anti-fuse transistors are shown in FIGS. 1 to 5b. 
Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
Anti-fuse memory can be utilized in all one time programmable applications, including RF-ID tags. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes. Therefore, IC manufacturing productivity can be increased by utilizing anti-fuse memory in combination with an RF communication interface on every wafer and/or every die on the wafer allowing for contact-less programming and reading chip specific or wafer specific information during IC manufacturing and packaging, as well as during printed circuit board assembly.
FIG. 1 is a circuit diagram illustrating the basic concept of an anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively, of the anti-fuse memory cell shown in FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low cost CMOS process.
FIG. 4a shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. Variants of this anti-fuse transistor are disclosed in commonly owned U.S. patent application Ser. No. 10/553,873 filed on Oct. 21, 2005, and commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007, the contents of which are incorporated by reference. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output MOS transistor with one floating diffusion terminal. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 4a is taken along the channel length of the device, which in the presently described example is a p-channel device. The channel is generally understood to be the area underneath an overlying polysilicon gate, having a length defined by edges of the polysilicon gate adjacent respective diffusion regions.
Anti-fuse transistor 30 includes a variable thickness gate oxide 32 formed on the substrate channel region 34, a polysilicon gate 36, sidewall spacers 38, a field oxide region 40 a diffusion region 42, and an LDD region 44 in the diffusion region 42. A bitline contact 46 is shown to be in electrical contact with diffusion region 42. The variable thickness gate oxide 32 consists of a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 42 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 36 and diffusion region 42 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In this example, the diffusion region 42 is connected to a bitline through a bitline contact 46, or other line for sensing a current from the polysilicon gate 36, and can be doped to accommodate programming voltages or currents. This diffusion region 42 is formed proximate to the thick oxide portion of the variable thickness gate oxide 32. To further protect the edge of anti-fuse transistor 30 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 38. This RPO is preferably used during the salicidiation process for preventing only a portion of diffusion region 42 and a portion of polysilicon gate 36 from being salicided. It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 42 will reduce leakage. Diffusion region 42 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse transistor 30 is shown in FIG. 4b. Bitline contact 46 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 4a. The active area 48 is the region of the device where the channel region 34 and diffusion region 42 is formed, which is defined by an OD mask during the fabrication process. The dashed outline 50 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 50 designates the regions where thick oxide is to be formed. OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first. Details of the CMOS process steps for fabricating anti-fuse transistor 30 will be discussed later. According to an embodiment of the present invention, the thin gate oxide area bounded by edges of the active area 48 and the rightmost edge of the OD2 mask, is minimized. In the presently shown embodiment, this area can be minimized by shifting the rightmost OD2 mask edge towards the parallel edge of active area 48. Commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007, the contents of which are incorporated by reference, describes alternate single transistor anti-fuse memory cells which can be used in a non-volatile memory array. Two transistor anti-fuse memory cells are known in the art, as shown in the example of FIGS. 5a and 5b. 
FIG. 5b shows a planar view of a two-transistor anti-fuse memory cell 60 having a minimized thin gate oxide area that can be manufactured with any standard CMOS process, according to an embodiment of the present invention. FIG. 5a shows a cross-sectional view of the memory cell 60 of FIG. 5b, taken along line B-B. Two-transistor anti-fuse memory cell 60 consists of an access transistor in series with an anti-fuse transistor. The access transistor includes a polysilicon gate 62 overlying a thick gate oxide 64, which itself is formed over the channel 66. On the left side of the channel 66 is a diffusion region 68 electrically connected to a bitline contact 70. On the right side of the channel 66 is a common diffusion region 72 shared with the anti-fuse transistor. The anti-fuse transistor includes a polysilicon gate 74 overlying a thin gate oxide 76, which itself is formed over the channel 78. The thick gate oxide 64 can correspond to that used for high voltage transistors while the thin gate oxide 76 can correspond to that used for low voltage transistors. The dashed outline 77 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 77 designates the regions where thick oxide is to be formed. While the right-most edge of dashed outline 77 is showed to be substantially aligned with an edge of the side-wall spacer adjacent to polysilicon gate 74, those skilled in the art will understand that this edge can be positioned anywhere between the sidewall spacers of polysilicon gates 62 and 74. It is well known that polysilicon gates 62 and 74 can be independently controlled, or alternatively can be connected to each other as shown in FIG. 5b. In the example of FIG. 5b, both polysilicon gates 62 and 74 are part of the same polysilicon structure, and connected to a wordline through wordline contact 80. Both diffusion regions 68 and 72 can have LDD regions, which can be identically doped or differently doped, depending on the desired operating voltages to be used. Commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007 describes alternate two-transistor anti-fuse memory cells which can be used in a non-volatile memory array.
The programming speed of OTP memories is relatively slow, since each programming cycle will attempt to program a certain number of data words at the same time. Following each programming cycle is a program verify cycle to ensure that the data words were successfully programmed. Any bits that do not pass the program verify step are reprogrammed. This process continues until all the memory cell states have been successfully programmed.
There are applications where the same data is to be programmed in every OTP memory. Boot block data for example, can be the same in every chip in the batch, while the actual user data can be different. The boot block can be programmed by the end user, or by the vendor. In either case, a significant number of program cycles will be required for programming this boot block data to all the OTP memory devices in the batch. There may be other applications where a portion of every OTP memory device will store the same data. In some cases, this data is not intended to be accessible or known by the end user, thereby requiring programming before delivery to the end user for integration into their systems. However, this pre-programming will add time overhead, which is undesired.
Mask ROM memory is a class of non-volatile memory which is programmed with data during the chip manufacturing stage. In a chip manufacturing stage, masks are used to define which memory cells in the memory array are to be permanently turned off. Since programming is performed during chip manufacturing, the effective “programming” speed is extremely high. This technique is cost effective with economies of scale, due to the capital cost of the mask sets that are required. For example, known video gaming console game cartridges used Mask ROM chips to store game data, and the fast manufacturing of the chips allowed for large quantities of game cartridges to be sold worldwide with minimal time.
Unfortunately, Mask ROM is programmable only at the manufacturing stage, and does not give end users the ability to program their own data to the memory device. U.S. Pat. No. 7,102,926 discloses a memory device whereby a Mask ROM memory array is paired with an electrically erasable programmable read only memory (EEPROM). However, there is additional complexity and cost associated with such a device because the manufacturing process for Mask ROM differs substantially from that of an EEPROM. Furthermore, the additional cost for an EEPROM device is not economical for applications in which data is only programmed to the memory once.
It is, therefore, desirable to provide a low cost OTP memory device which is mask programmable while having user programmability.